The present invention relates to a frequency divider for use in a semiconductor integrated circuit.
The frequency divider is used, for example, in a part of a frequency divider of the type in which the ratio of an input frequency to an output frequency is a fractional value is hereinafter referred to as "fractional frequency divider". Such fractional frequency divider is extremely effective in that a lockup time can be reduced, because the reference signal frequency can be set to a high value compared with a phase-locked loop using a frequency divider of a type in which the above-mentioned division value is an integer.
The operation of a conventional fractional frequency divider will be described with reference to FIG. 8. In the factional frequency divider, a "dividing number" defined by the ratio of the input frequency to the output frequency has two programmable states of M and M+1 (M is a given integer). In the fractional frequency divider, the dividing number M or M+1 is controlled in each period as shown in the timing chart of FIG. 8. In the figure, a unit operation period T is divided into segments by an integer N. The segment that has the dividing number M+1 is controlled to occur once so as to occur at the same time in each unit operation period T. In FIG. 8, the time points in the unit operation period T are numbered 0, 1, . . . , N-2 and N-1. Here, the time point is a point of time in each period when the unit operation period T is divided into the number, N. The average dividing number M' in one unit operation period T is given by the following expression: EQU M'={(M+1)+(N-1).times.M}/N=M+1/N.
The fractional frequency divider whose dividing number is a given fraction is thus realized.
In the above-described fractional frequency divider, as shown in the frequency spectrum distribution of the division output of FIG. 9, when an input signal with a frequency fo is frequency-divided by the average dividing number M', strong spurious spectrum components with a frequency fo/M'.+-.fs (here, fs=1/T) are generated as well as signal components with the divided frequency fo/M' in the division output. This is because the fractional frequency divider repeats the same operation in the fixed operation period T.